A typical semiconductor memory comprises of a large number of memory cells arranged in an array of rows and columns. Each memory cell is capable of storing therein a binary digit, a binary “one” or a binary “zero”. Each row of the memory cell array is typically connected to a word line and each column of the memory cell array is typically connected to a pair of bit lines. Read and write operations are performed on an individual memory cell by addressing the appropriate row of the array using the word lines and addressing the appropriate cell in the addressed row using the bit lines. Depending upon the signals applied to the bit lines, a read operation may be performed for accessing binary data stored in the addressed memory cell or write operation may be performed for storing binary data in the addressed memory cell. In order to ensure that the read and write operations are properly performed, a time delay is present between the accessing of memory cell and read/write operation. As a result of this, a delay circuit is incorporated in almost all memory devices used at present. This delay circuit provides a timing delay to enable successful read and write operations in the memory device. In particular, for the case of writing data into a memory cell, this timing delay corresponds to the time required for a written memory cell to stabilize. The required time delay can be determined if the memory structure and its likely behavior is well known. However, the memory behavior depends on many factors such as memory size and PVT (process voltage and temperature conditions). Moreover, since different process tolerances are involved in the manufacture of memories, this means that any two memories may not have identical behavior. Therefore, the time delay required for proper functioning of a memory device cannot be predetermined.
To overcome the above mentioned problems, the concept of ‘dummy cells’ has been successfully used in semiconductor memory devices. These cells are provided in the memory region of the semiconductor device and have same structure as the actual memory cells. As a result, it takes same time for writing data into dummy cell as taken in the case of normal memory cell. This fact can be exploited to make the timing circuit responsive to the operating conditions of the memory.
In one of the configurations commonly used, the memory device is provided with a column of dummy cells. Dummy data is written in one of these dummy cells whereas other dummy cells are kept inactive for the purpose of loading. During the write operation, this dummy cell is accessed and data is written into it by a write driver. Simultaneously, in the memory array, a normal memory cell is accessed and data is written into it by another write driver. As soon as the voltage in the written dummy cell rises to the voltage corresponding to the written data, a write reset (W-reset) signal is initiated to indicate successful completion of write operation. The recovery operation for the next cycle starts in response to this signal.
However, since in this configuration dummy data is written only in one dummy cell, the self timing of the device depends almost entirely on the behavior of this dummy cell. Also, there is a mismatch between behavior of a normal memory cell and dummy cell due to presence of load on the internal node of the dummy cell.